1. Field of the Invention
This invention relates generally to the elimination of possible voiding of etch resistant material in vias in semiconductor device fabrication. In particular, this invention relates to the elimination of voiding of spin-on bottom anti-reflection coating (BARC) material in vias using electron beam (e-beam) flood exposure in semiconductor device fabrication.
2. Description of the Related Art
In certain processes of making semiconductor devices, a via or hole is etched through an insulating dielectric layer to expose an underlying layer, and the insulating dielectric layer is then etched again to form a wider trench above the via or contact hole. For example, in a typical dual damascene process, via holes and overlying trenches connecting the via holes are formed in an inter-level dielectric (ILD). The trench and vias are then filled with a conductive material that connects to underlying conducting material on the device through the via holes. The via hole is first etched in a hole formation etch, and then exposed to a second etch in the trench formation etch. In this case, the second etch exposes any layer exposed by the hole to the etchant in the second etch.